• Five platforms LX, LXT, SXT, TXT, and FXT
− Virtex-5 LX: High-performance general logic applications
− Virtex-5 LXT: High-performance logic with advanced serial connectivity
− Virtex-5 SXT: High-performance signal processing applications with advanced serial connectivity
− Virtex-5 TXT: High-performance systems with double density advanced serial connectivity
− Virtex-5 FXT: High-performance embedded systems with advanced serial connectivity
• Cross-platform compatibility
− LXT, SXT, and FXT devices are footprint compatible in the same package using adjustable voltage regulators
• Most advanced, high-performance, optimal-utilization,FPGA fabric
− Real 6-input look-up table (LUT) technology
− Dual 5-LUT option
− Improved reduced-hop routing
− 64-bit distributed RAM option
−SRL32/Dual SRL16 option
• Powerful clock management tile (CMT) clocking
− Digital Clock Manager (DCM) blocks for zero delay buffering, frequency synthesis, and clock phase shifting
− PLL blocks for input jitter filtering, zero delay buffering, frequency synthesis, and phase-matched clock division
• 36-Kbit block RAM/FIFOs
− True dual-port RAM blocks
− Enhanced optional programmable FIFO logic
− Programmable
- True dual-port widths up to x36
- Simple dual-port widths up to x72
− Built-in optional error-correction circuitry
− Optionally program each block as two independent 18-Kbit blocks
• High-performance parallel SelectIO technology
− 1.2 to 3.3V I/O Operation
− Source-synchronous interfacing using ChipSync™ technology
− Digitally-controlled impedance (DCI) active termination
− Flexible fine-grained I/O banking
− High-speed memory interface support
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• Advanced DSP48E slices
− 25 x 18, two’s complement, multiplication
− Optional adder, subtracter, and accumulator
− Optional pipelining
− Optional bitwise logical functionality
− Dedicated cascade connections
• Flexible configuration options
− SPI and Parallel FLASH interface
− Multi-bitstream support with dedicated fallback reconfiguration logic
− Auto bus width detection capability
• System Monitoring capability on all devices
− On-chip/Off-chip thermal monitoring
− On-chip/Off-chip power supply monitoring
− JTAG access to all monitored quantities
• Integrated Endpoint blocks for PCI Express Designs
− LXT, SXT, TXT, and FXT Platforms
− Compliant with the PCI Express Base Specification 1.1
− x1, x4, or x8 lane support per block
− Works in conjunction with RocketIO™ transceivers
• Tri-mode 10/100/1000 Mb/s Ethernet MACs
− LXT, SXT, TXT, and FXT Platforms
− RocketIO transceivers can be used as PHY or connect to external PHY using many soft MII (Media Independent Interface) options
• RocketIO GTP transceivers 100 Mb/s to 3.75 Gb/s
− LXT and SXT Platforms
• RocketIO GTX transceivers 150 Mb/s to 6.5 Gb/s
− TXT and FXT Platforms
• PowerPC 440 Microprocessors
− FXT Platform only
− RISC architecture
− 7-stage pipeline
− 32-Kbyte instruction and data caches included
− Optimized processor interface structure (crossbar)
• 65-nm copper CMOS process technology
•1.0V core voltage
•High signal-integrity flip-chip packaging available in standard or Pb-free package options
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Virtex-5 FPGA Data Sheet: DC and Switching Characteristics (DS202)
This data sheet contains the DC and Switching Characteristic specifications for the Virtex-5 family.
Virtex-5 FPGA User Guide (UG190) This guide includes chapters on:
•Clocking Resources
•Clock Management Technology (CMT)
•Phase-Locked Loops (PLL)
•Block RAM
•Configurable Logic Blocks (CLBs)
•SelectIO Resources
•SelectIO Logic Resources
•Advanced SelectIO Logic Resources
Virtex-5 FPGA XtremeDSP Design Considerations (UG193)
This guide describes the DSP48E slice and includes reference designs for using DSP48E math functions and various filters.
Virtex-5 FPGA Configuration Guide (UG191)
This all-encompassing configuration guide includes chapters on configuration interfaces (serial and parallel), multi-bitstream management, bitstream encryption, Boundary-Scan and JTAG configuration, and reconfiguration techniques.
Virtex-5 FPGA Packaging and Pinout Specification(UG195)
This specification includes the tables for device/package combinations and maximum I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and thermal specifications.
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Virtex-5 FPGA PCB Designer’s Guide (UG203)
This guide provides information on PCB design for Virtex-5 devices, with a focus on strategies for making design decisions at the PCB and interface level.
Virtex-5 FPGA System Monitor User Guide (UG192)
The System Monitor functionality is outlined in this guide.
Virtex-5 FPGA RocketIO GTP Transceiver User Guide (UG196)
This guide describes the RocketIO GTP transceivers available in the Virtex-5 LXT and SXT platforms.
Virtex-5 FPGA RocketIO GTX Transceiver User Guide (UG198) This guide describes the RocketIO GTX transceivers available in the Virtex-5 TXT and FXT platforms.
Virtex-5 FPGA Tri-Mode Ethernet MAC User Guide (UG194) This guide describes the dedicated Tri-Mode Ethernet Media Access Controller available in the Virtex-5 LXT, SXT, TXT, and FXT platforms.
Virtex-5 FPGA Integrated Endpoint Block for PCI Express Designs User Guide (UG197)
This guide describes the integrated Endpoint blocks in the Virtex-5 LXT, SXT, TXT, and FXT platforms that are PCI Express compliant.
Embedded Processor Block in Virtex-5 FPGAs Reference Guide (UG200)
This reference guide is a description of the embedded processor block available in the Virtex-5 FXT platform.
|
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics (DS202)
This data sheet contains the DC and Switching Characteristic specifications for the Virtex-5 family.
Virtex-5 FPGA User Guide (UG190) This guide includes chapters on:
•Clocking Resources
•Clock Management Technology (CMT)
•Phase-Locked Loops (PLL)
•Block RAM
•Configurable Logic Blocks (CLBs)
•SelectIO Resources
•SelectIO Logic Resources
•Advanced SelectIO Logic Resources
Virtex-5 FPGA XtremeDSP Design Considerations (UG193)
This guide describes the DSP48E slice and includes reference designs for using DSP48E math functions and various filters.
Virtex-5 FPGA Configuration Guide (UG191)
This all-encompassing configuration guide includes chapters on configuration interfaces (serial and parallel), multi-bitstream management, bitstream encryption, Boundary-Scan and JTAG configuration, and reconfiguration techniques.
Virtex-5 FPGA Packaging and Pinout Specification(UG195)
This specification includes the tables for device/package combinations and maximum I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and thermal specifications.
|
Virtex-5 FPGA PCB Designer’s Guide (UG203)
This guide provides information on PCB design for Virtex-5 devices, with a focus on strategies for making design decisions at the PCB and interface level.
Virtex-5 FPGA System Monitor User Guide (UG192)
The System Monitor functionality is outlined in this guide.
Virtex-5 FPGA RocketIO GTP Transceiver User Guide (UG196)
This guide describes the RocketIO GTP transceivers available in the Virtex-5 LXT and SXT platforms.
Virtex-5 FPGA RocketIO GTX Transceiver User Guide (UG198) This guide describes the RocketIO GTX transceivers available in the Virtex-5 TXT and FXT platforms.
Virtex-5 FPGA Tri-Mode Ethernet MAC User Guide (UG194) This guide describes the dedicated Tri-Mode Ethernet Media Access Controller available in the Virtex-5 LXT, SXT, TXT, and FXT platforms.
Virtex-5 FPGA Integrated Endpoint Block for PCI Express Designs User Guide (UG197)
This guide describes the integrated Endpoint blocks in the Virtex-5 LXT, SXT, TXT, and FXT platforms that are PCI Express compliant.
Embedded Processor Block in Virtex-5 FPGAs Reference Guide (UG200)
This reference guide is a description of the embedded processor block available in the Virtex-5 FXT platform.
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