• Three sub-families:
• Virtex-6 LXT FPGAs: High-performance logic with
advanced serial connectivity
• Virtex-6 SXT FPGAs: Highest signal processing
capability with advanced serial connectivity
• Virtex-6 HXT FPGAs: Highest bandwidth serial
connectivity
• Compatibility across sub-families
• LXT and SXT devices are footprint compatible in
the same package
• Advanced, high-performance FPGA Logic
• Real 6-input look-up table (LUT) technology
• Dual LUT5 (5-input LUT) option
• LUT/dual flip-flop pair for applications requiring rich
register mix
• Improved routing efficiency
• 64-bit (or two 32-bit) distributed LUT RAM option
per 6-input LUT
• SRL32/dual SRL16 with registered outputs option
• Powerful mixed-mode clock managers (MMCM)
• MMCM blocks provide zero-delay buffering,
frequency synthesis, clock-phase shifting, input
jitter filtering, and phase-matched clock division
• 36-Kb block RAM/FIFOs
• Dual-port RAM blocks
• Programmable
- Dual-port widths up to 36 bits
- Simple dual-port widths up to 72 bits
• Enhanced programmable FIFO logic
• Built-in optional error-correction circuitry
• Optionally use each block as two independent
18 Kb blocks
• High-performance parallel SelectIO™ technology
• 1.2 to 2.5V I/O operation
• Source-synchronous interfacing using
ChipSync™ technology
• Digitally controlled impedance (DCI) active
termination
• Flexible fine-grained I/O banking
• High-speed memory interface support with
integrated write-leveling capability
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• Advanced DSP48E1 slices
• 25 x 18, two's complement multiplier/accumulator
• Optional pipelining
• New optional pre-adder to assist filtering
applications
• Optional bitwise logic functionality
• Dedicated cascade connections
• Flexible configuration options
• SPI and Parallel Flash interface
• Multi-bitstream support with dedicated fallback
reconfiguration logic
• Automatic bus width detection
• System Monitor capability on all devices
• On-chip/off-chip thermal and supply voltage
monitoring
• JTAG access to all monitored quantities
• Integrated interface blocks for PCI Express® designs
• Compliant to the PCI Express Base Specification
2.0
• Gen1 (2.5 Gb/s) and Gen2 (5 Gb/s) support with
GTX transceivers
• Endpoint and Root Port capable
• x1, x2, x4, or x8 lane support per block
• GTX transceivers: up to 6.6 Gb/s
• Data rates below 480 Mb/s supported by
oversampling in FPGA logic.
• GTH transceivers: 2.488 Gb/s to beyond 11 Gb/s
• Integrated 10/100/1000 Mb/s Ethernet MAC block
• Supports 1000BASE-X PCS/PMA and SGMII
using GTX transceivers
• Supports MII, GMII, and RGMII using SelectIO
technology resources
• 2500Mb/s support available
• 40 nm copper CMOS process technology
• 1.0V core voltage (-1, -2, -3 speed grades only)
• Lower-power 0.9V core voltage option (-1L speed
grade only)
• High signal-integrity flip-chip packaging available in
standard or Pb-free package options
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Virtex-6 FPGA Data Sheet: DC and Switching
Characteristics (DS152)
This data sheet contains the DC and Switching
Characteristic specifications for the Virtex-6 family.
Virtex-6 FPGA Packaging and Pinout Specifications
(UG365)
These specifications includes the tables for device/package
combinations and maximum I/Os, pin definitions, pinout
tables, pinout diagrams, mechanical drawings, and thermal
specifications.
Virtex-6 FPGA Configuration Guide (UG360)
This all-encompassing configuration guide includes
chapters on configuration interfaces (serial and parallel),
multi-bitstream management, bitstream encryption,
boundary-scan and JTAG configuration, and reconfiguration
techniques.
Virtex-6 FPGA SelectIO Resources User Guide (UG361)
This guide describes the SelectIO™ resources available in
all the Virtex-6 devices.
Virtex-6 FPGA Clocking Resources User Guide (UG362)
This guide describes the clocking resources available in all
the Virtex-6 devices, including the MMCM and clock buffers.
Virtex-6 FPGA Memory Resources User Guide (UG363)
This guide describes the Virtex-6 device block RAM and
FIFO capabilities.
Virtex-6 FPGA CLB User Guide (UG364)
This guide describes the capabilities of the configurable
logic blocks (CLB) available in all Virtex-6 devices.
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Virtex-6 FPGA GTX Transceivers User Guide (UG366)
This guide describes the GTX transceivers available in all
the Virtex-6 FPGAs except the XC6VLX760.
Virtex-6 FPGA GTH Transceivers User Guide (UG371)
This guide describes the GTH transceivers available in all
Virtex-6 HXT FPGAs except the XC6VHX250T and the
XC6VHX380T in the FF1154 package.
Virtex-6 FPGA DSP48E1 Slice User Guide (UG369)
This guide describes the architecture of the DSP48E1 slice
in Virtex-6 FPGAs and provides configuration examples.
Virtex-6 FPGA Tri-Mode Ethernet MAC User Guide
(UG368)
This guide describes the dedicated tri-mode Ethernet
media access controller (TEMAC) available in all the
Virtex-6 FPGAs except the XC6VLX760.
Virtex-6 FPGA System Monitor User Guide (UG370)
This guide describes the System Monitor functionality.
Virtex-6 FPGA PCB Design Guide (UG373)
This guide provides information on PCB design for Virtex-6
devices, with a focus on strategies for making design
decisions at the PCB and interface level.
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